Symmetric high-voltage p-channel LDMOS transistors show a high on-resistance compared to that of asymmetric p-channel LDMOS transistors. This is mainly due to the large cell-pitch and the large channel-length of the device. In general, the punch-through behavior between two p-drift regions is the limiting factor regarding a reduction of the channel-length.
Furthermore, a low threshold voltage of symmetric high-voltage p-channel transistors is desired and achieved by a relatively low doping concentration of the body well. The low doping concentration between the two p-drift regions increases the danger of a punch-through. Therefore, the minimal channel-length of the symmetric p-channel LDMOS transistor is typically much larger than that of an asymmetric p-channel LDMOS tranistor.
If the body-well doping is not to be increased, a reduction of the channel-length is only possible by a reduction of the depth of the p-well defining the p-drift region or by an implantation of a relatively low dose of p-dopants forming a lightly doped drain. These methods are avoided because they are not in accordance with the conventional production processes or require dedicated process steps.